Self-biased high voltage level shifter

ABSTRACT

A high voltage level shifter having a cost effective design that saves chip architecture and power. The high voltage level-shifter includes a resistor connected between a first node and a first power supply rail. An inverter couples to receive an input signal to provide an inverted input signal. A first circuit portion couples to receive the inverted input signal and connects between the first power supply rail and a second power supply rail for converting a high voltage signal into a low voltage signal. The first circuit portion includes a first clamp circuit, wherein the first circuit portion is biased through the first clamp circuit and the first node. A second circuit portion couples to receive the input signal and connects between the first power supply rail and a second power supply rail for converting a low voltage signal into a high voltage signal. The second circuit portion includes a second clamp circuit, wherein the second circuit portion is biased through the second clamp circuit and the first node. The second circuit portion provides a first internal bias for the first circuit portion and the first circuit portion provides a second internal bias for the second circuit portion. This high voltage level-shifter provides level shifting a low voltage signal (&lt;5V) to a high voltage signal (˜40V), with no static power dissipation while still protecting all devices.

FIELD OF THE INVENTION

The present invention relates to level shifters and, more particularly,a self-biased high voltage level shifter.

BACKGROUND OF THE INVENTION

Many integrated circuits, such as display drivers, require a combinationof high-voltage driving capability (an output voltage swing up to 100Vor more) and a digital control using standard 5V CMOS logic. Hence,complex level-shifting circuits are needed to convert the 5V controlsignals into the desired high-voltage output waveforms. Moreover, inmany of those applications, the system is battery-powered and verysevere constraints are put on the power consumption of thelevel-shifters. One application where both high-voltage drivingcapability and low power consumption are required in the design ofdriver chips is in automotive applications.

Level shifters, in general, are utilized in a circuit to transition froma low voltage signal to a high voltage signal. In the alternative, alevel shifter may be used to transition from a high voltage signal to alow voltage signal. Level shifters are commonly used for multi-rail ormulti-power supply designs, where multiple rails or multiple powersupplies exist and numerous signals reference these multiple rails orpower supplies. These signals interact with various logic blocks thatoperate on different power supplies. Thus, every time a high voltagesignal is transferred to a low voltage block, the signal must belevel-shifted. Similarly, in the alternative, when a low-voltage signalis transferred to a high voltage block, the signal must belevel-shifted.

Most of the circuits in the automotive electronic systems are highvoltage circuits. High voltage level shifters, however, are large. Inaddition, when there are a lot of signals that need to be level-shifted,it becomes very difficult to incorporate large level shifters in asystem's design. Thus, to date, there has been no way of designingaround the affects of incorporating high voltage level shifters in asystem. In particular, high-voltage signals in a electronic system leadsto high-voltage components which are larger than low-voltage components.Secondly, another deficiency of high-voltage level-shifters is that theyare slow. Primarily, because the high-voltage components are large,these components cannot be switched as fast as low-voltage components.

Referring to known a high-voltage level-shifter 10 as is displayed FIG.1, a low-voltage input signal IN₁ is level-shifted to an high voltageoutput signal Out₁. Transistors, MN₁ and MN₂, provide the level shiftingfunction to shift a voltage applied at the input signal node IN₁ to asignal at the output node Out₁. Transistors, MP₁ and MP₂, protect thedrain-to-source voltage V_(ds) and gate-to-source voltage V_(gs) oftransistors, MP₄ and MP₃. Diodes, D₂ and D₁, only provide protection forthe gate-to-source voltage V_(gs) of transistors, MP₂ and MP₁. A highvoltage reference HV_(ref1) is applied to gate of transistors, MP₂ andMP₁, such that the source of each transistor, MP₂ and MP₁, will not goone gate-to-source voltage V_(gs) above the HV_(ref1) signal. Thisdesign for a high voltage level-shifter is troublesome in that itrequires a large and complex circuit to provide a high voltage referenceHV_(ref1).

FIG. 2 shows the another known level-shifter 20 that is self-biased,wherein a low-voltage input signal IN₂ is level shifted to an highvoltage output signal Out₂. Transistors, MN₃ and MN₄, are switched onand off to provide the level-shifting feature of level-shifter 20.Transistors, MP₆ and MP₅, protect the drain-to-source voltage V_(ds) andgate-to-source voltage V_(gs) of transistors, MP₈ and MP₇. As shown, acurrent source I₁ is pulled through two reverse bias Zener diodes, D₄and D₃, which have a 6.5V breakdown voltage for this particulartechnology. Those skilled in the art would recognize that even if aZener diode has a 13V breakdown voltage, the only requirement is thatthe breakdown voltages of diodes, D₄ and D₃, must correspond with thev_(gs) of transistors, MP₅ and MP₆. Diodes, D₄ and D₃, provide the highvoltage reference signal which is applied to each gate of transistors,MP₅ and MP₆, such that the source of each transistor, MP₅ and MP₆, willnot go one gate-to-source voltage V_(gs) above the high voltagereference signal.

The difference between the design of high voltage level-shifter 20 andthe design of the level-shifter 10 in FIG. 1 is the way in which thehigh voltage reference signal HV_(ref1) is generated. This approach,however, requires the external current source I₁.

Thus, there exists a need for a self-biased high voltage level shifterthat provides level shifting a low voltage signal (<5V) to a highvoltage signal (˜40V), with no static power dissipation while stillprotecting all devices. Furthermore, there exists a need for a simple,yet, cost-effective design that does not require an external currentsource.

The present invention is directed to overcoming, or at least reducingthe effects of one or more of the problems set forth above.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentsome concepts of the invention in a simplified form as a prelude to themore detailed description that is presented later.

To address the above-discussed deficiencies of high voltage levelshifters, the present invention teaches a high voltage level-shifterhaving a novel, simple design that provides level shifting a low voltagesignal (<5V) to a high voltage signal (˜40V), with no static powerdissipation while still protecting all devices.

The high voltage level-shifter includes a resistor connected between afirst node and a first power supply rail. An inverter couples to receivean input signal to provide an inverted input signal. A first circuitportion couples to receive the inverted input signal and connectsbetween the first power supply rail and a second power supply rail forconverting a high voltage signal into a low voltage signal. The firstcircuit portion includes a first clamp circuit, wherein the firstcircuit portion is biased through the first clamp circuit and the firstnode. A second circuit portion couples to receive the input signal andconnects between the first power supply rail and a second power supplyrail for converting a low voltage signal into a high voltage signal. Thesecond circuit portion includes a second clamp circuit, wherein thesecond circuit portion is biased through the second clamp circuit andthe first node. The second circuit portion provides a first internalbias for the first circuit portion and the first circuit portionprovides a second internal bias for the second circuit portion.

The first circuit portion includes a first N-type transistor connectedbetween a second node and a first power supply rail. The first N-typetransistor is biased by the inverted input signal. A first P-typetransistor connects between the second node and a fourth node. The firstP-type transistor is biased by the first clamp circuit at the firstnode. A second P-type transistor connects between a second power supplyrail and the fourth node which provides the output signal. The secondP-type transistor is biased by the first internal bias provided by thesecond circuit portion.

The second circuit portion includes a first N-type transistor connectedbetween a second node and a first power supply rail. The first N-typetransistor is biased by the input signal. A first P-type transistorconnects between the second node and a fourth node. The first P-typetransistor is biased by the second clamp circuit at the first node. Asecond P-type transistor connects between a second power supply rail andthe fourth node which provides the output signal. The second P-typetransistor is biased by the second internal bias provided by the firstcircuit portion.

The first and second clamp circuits each may include a series connectedpair of diodes, whereby the integrated bias current though each clampcircuit protects the first P-type transistor in each of the first andsecond circuit portions.

The advantages of this solution is that the implementation is smallerthan previous solutions where there are fewer components tied to thepower supply rail or battery. In addition, there is only static powerdissipation when the voltage is above the clamp voltage.

The following description and annexed drawings set forth in detailcertain illustrative aspects and implementations of the invention. Theseare indicative of but a few of the various ways in which the principlesof the invention may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following descriptiontaken in conjunction with the accompanying drawings in which likereference numbers indicate like features and wherein:

FIG. 1 is a known high voltage level-shifter;

FIG. 2 illustrates a known self-biased high voltage level-shifter; and

FIG. 3 displays a self-biased high voltage level-shifter in accordancewith the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

One or more exemplary implementations of the present invention will nowbe described with reference to the attached drawings, wherein likereference numerals are used to refer to like elements throughout. Thevarious aspects of the invention are illustrated below in a high voltagelevel shifter, although the invention and the appended claims are notlimited to the illustrated examples.

The present invention is best understood by comparison with the priorart. Hence, this detailed description begins with a discussion of knownhigh voltage level shifter as is shown in FIG. 1. As shown, alow-voltage input signal IN₁ is level-shifted to an high voltage outputsignal Out₁. Transistors MN₂ and MN₁ are switched on and off, whereinwhen transistor MN₂ is on, transistor MN₁ is off. The converse is alsotrue. In the instance, where input signal IN₁ is a high signal,transistor MN₁ will turn on. Current will flow through the drain node oftransistor MN₁ which pull down the gate of transistor MP₄. Since thegate of transistor MP₄ is pulled down, the gate-to-source voltage V_(gs)of transistor MP₄ opens up and turns on transistor MP₄ very hard,pulling the signal Out₁ up. Thereby, when the signal IN₁ goes high, thesignal Out₁ goes up. When signal IN₁ goes low, transistor MN₂ turns on,wherein current flows through transistors, MP₂ and MP₃. The purpose oftransistors, MP₂ and MP₁, is to protect the drain-to-source voltageV_(ds) and gate-to-source voltage V_(gs) of transistors, MP₄ and MP₃.Diodes, D₂ and D₁, only provide protection for the gate-to-sourcevoltage V_(gs) of transistors, MP₂ and MP₁. A high voltage referenceHV_(ref1) is applied to gate of transistors, MP₂ and MP₁, such that thesource of each transistor, MP₂ and MP₁, will not go one gate-to-sourcevoltage V_(gs) above the HV_(ref1) signal. A large and complex circuitis conventional used to generate the high voltage reference HV_(ref1).

FIG. 2 shows the another known self-biased level shifter, wherein alow-voltage input signal IN₂ is level shifted to an high voltage outputsignal Out₂. Input signal IN₂ is inverted by inverter 22. Signal IN₂ andthe inverted version of signal IN₂ couples to the gate of transistors,MN₃ and MN₄, respectively. Transistors, MN₃ and MN₄, are switched on andoff, wherein when transistor MN₃ is on, transistor MN₄ is off.Accordingly, the converse is true. When input signal IN₂ is a highsignal, transistor MN₃ turns on. Current flows through the drain oftransistor MN₃ which pull down the gate of transistor MP₈. Since thegate of transistor MP₈ is pulled down, the gate-to-source voltage V_(gs)of transistor MP₈ opens up and turns transistor MP₈ on fully, pullingthe signal Out₂ up. Thereby, when the input signal IN₂ goes high, thesignal Out₂ increases. When signal IN₂ is low, transistor MN₄ turns on,wherein current flows through transistors, MP₆ and MP₇. The purpose oftransistors, MP₆ and MP₅, is to protect the drain-to-source voltageV_(ds) and gate-to-source voltage V_(gs) of transistors, MP₈ and MP₇. Asshown a current source 11 is pulled through two reverse bias Zenerdiodes, D₄ and D₃, which have a 6.5V breakdown voltage for thisparticular technology. Those skilled in the art would recognize thateven if a Zener diode has a 13V breakdown voltage, the only requirementis that the breakdown voltages of diodes, D₄ and D₃, must correspondwith the V_(gs) of transistors, MP₆ and MP₅. Diodes, D₄ and D₃, providethe high voltage reference signal which is applied to each gate oftransistors, MP₆ and MP₅, such that the source of each transistor, MP₆and MP₅, will not go one gate-to-source voltage V_(gs) above the highvoltage reference signal. The difference between this design and thedesign of the level-shifter in FIG. 1 is the way in which the highvoltage reference signal HV_(ref1) is generated. Optionally, a capacitorC₁ may AC couple the output Out₂ to ensure that there are no highvoltage transients on the output signal Out₂ such that the output signalOut₂ is reflective of any changes in supply voltage V_(SS). Thisapproach, however, has static power dissipation. In addition, thisapproach requires an external current source I₁, wherein an idealcurrent source I₁ is utilized. In an actual application, however, noideal current source exists, but rather current must be suppliedexternal to the device. This requirement creates a substantialdisadvantage for this design.

FIG. 3 illustrates a level shifting structure in accordance with thepresent invention. This high voltage level-shifter is self-biased anddoes not have the requirement of an external current source. Thissolution provides a novel circuit and method for setting up the highvoltage reference. As opposed to FIGS. 1 and 2, this implementation doesnot need any external current reference nor a large amount of circuitryto set up a high voltage reference.

As shown, a low-voltage input signal IN₃ is level shifted to an highvoltage output signal Out₂. Input signal IN₃ is inverted by inverter 32.Signal IN₃ and the inverted version of signal IN₃ couples to the gate oftransistors, MN₅ and MN₆, respectively. Transistors, MN₅ and MN₆, areswitched on and off, wherein when transistor MN₅ is on, transistor MN₆is off. Accordingly, the converse is true. As such, transistors, MN₆ andMN₅, perform the level-shifting function. The high voltage reference isset up on the gate of transistors, MP₉ and MP₁₀, through diodes, D₅ andD₆, or D₇ and D₈, respectively, which are reversed biased through theresistor R₁. If input signal IN₃ is high, transistor MN₆ will turn onand pull the gate of transistor MP₁₁ low which is connected to the drainof transistor MP₁₂. Thereby transistor MP₁₁ turns on and current flowsthrough transistor MP₁₁. This pulls the drain of transistor MP₁₁ high.The drain of transistor MP₁₁ will only increase as high as the Zenerbreakdown of diodes, D₅ and D₆, allow it to increase. Once the breakdownof the transistors that make up diodes, D₅ and D₆, are met, currentbegins to flow through diodes, D₅ and D₆, which is limited by resistorR₁.

In the alternative, when input signal IN₃ is low, transistor MN₁₁ willturn on and pull the gate of transistor MP₁₂ low which is connected tothe drain of transistor MP₁₁. Thereby, transistor MP₁₂ turns on andcurrent flows through transistor MP₁₂. As a result, the drain oftransistor MP₁₂ is pulled high. The drain of transistor MP₁₂, however,will only increase as high as the Zener breakdown of diodes, D₇ and D₈,allow it to increase. Once the breakdown of the transistors that make updiodes, D₇ and D₈, are met, current begins to flow through diodes, D₇and D₈, which is limited by resistor R₁. Thereby, transistors, MP₉ andMP₁₀, will always be protected because transistors, MN₅ and MN₆, arealways on and out of phase. This guarantees a high voltage reference atall times.

Specifically, the high voltage reference is set up using resistor R₁connected to diodes, D₅ and D₆, or, in the alternative, diodes, D₇ andD₈. Particularly, as soon as the reverse breakdown of diodes, D₅ and D₆,is met, current flows through the diodes, D₅ and D₆, and through theresistor R₁ which sets up a voltage at the gate of transistor MP₉. Thisvoltage is related to the reverse breakdown of the Zener diodes, D₅ andD₆. Therefore, as the voltage at the drain of transistor MP₁, increases,the breakdown of the two diodes, D₅ and D₆, is met. As a result, currentbegins to flow through diodes, D₅ and D₆, and the gate of transistor MP₉begins to rise. For example, if the voltage at the drain of transistorMP₁₁, rises to 50V, the gate of transistor MP₉ would only be 13V below50V. In the alternative, for example, if the voltage at the drain oftransistor MP₁₁ decreases to another voltage, the gate of transistor MP₉would only be 13V below the same voltage at the drain of transistorMP₁₁.

In the alternative, the high voltage reference is set up using resistorR₁ connected to diodes, D₇ and D₈. Specifically, as soon as the reversebreakdown of diodes, D₇ and D₈, is met, current flows through thediodes, D₇ and D₈, and through the resistor R₁ which sets up a voltageat the gate of transistor MP₁₀. This voltage is related to the reversebreakdown of the Zener diodes, D₇ and D₈. Therefore, as the voltage atthe drain of transistor MP₁₂ increases, the breakdown of the two diodes,D₇ and D₈, is met, current begins to flow through the diodes, D₇ and D₈,and the gate of transistor MP₁₀ begins to rise. If the voltage at thedrain of transistor MP₁₂, for example, rises to 50V, the gate oftransistor MP₁₀ would only be 13V below 50V. If the voltage at the drainof transistor MP₁₂, for example, decreases to another voltage, the gateof transistor MP₁₀ would only be 13V below the same voltage at the drainof transistor MP₁₂.

Advantages of the high voltage level shifter in accordance with thepresent invention include, but are not limited to, a high voltagelevel-shifter having a cost effective design that chip architecture (orreal estate) and power. The high voltage level-shifter in accordancewith the present invention is smaller than previous solutions wherethere are fewer components tied to the power supply rail or battery. Inaddition, there is only static power dissipation when the voltage isabove the clamp voltage.

While the principles of the present invention have been demonstratedwith particular regard to the structures and methods disclosed herein,it will be recognized that various departures may be undertaken in thepractice of the invention. The scope of the invention is not intended tobe limited to the particular structures and methods disclosed herein,but should instead be gauged by the breadth of the claims that follow.

Those of skill in the art will recognize that the physical location ofthe elements illustrated in FIG. 3 can be moved or relocated whileretaining the function described above.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference.

All the features disclosed in this specification (including anyaccompany claims, abstract and drawings) may be replaced by alternativefeatures serving the same, equivalent or similar purpose, unlessexpressly stated otherwise. Thus, unless expressly stated otherwise,each feature disclosed is one example only of a generic series ofequivalent or similar features.

The terms and expressions which have been employed in the foregoingspecification are used therein as terms of description and not oflimitation, and there is no intention in the use of such terms andexpressions of excluding equivalents of the features shown and describedor portions thereof, it being recognized that the scope of the inventionis defined and limited only by the claims which follow.

1. A high voltage level shifter, the high voltage level shifter couplesto receive an input signal to generate an output signal, comprising: aresistor coupled between a first node and a first power supply rail; aninverter coupled to receive the input signal to generate an invertedinput signal; a first circuit portion coupled between the first powersupply rail and a second power supply rail for converting a high-voltagesignal into a low-voltage signal, the first circuit portion includes afirst clamp circuit, wherein the first circuit portion is biased throughthe first clamp circuit and the first node, the first circuit portioncoupled to receive the inverted input signal; and a second circuitportion coupled between the first power supply rail and the second powersupply rail for converting a low-voltage signal into a high-voltagesignal, the second circuit portion includes a second clamp circuit,wherein the second circuit portion is biased through the second clampcircuit and the first node, the second circuit portion coupled toreceive the input signal, wherein the second circuit portion provides afirst internal bias for the first circuit portion and the first circuitportion provides a second internal bias for the second circuit portion.2. The high voltage level shifter of claim 1, wherein the first circuitportion comprises: a first N-type transistor coupled between a secondnode and a first power supply rail, the first N-type transistor biasedby the inverted input signal; a first P-type transistor coupled betweenthe second node and a fourth node, the first P-type transistor biased bythe first clamp circuit at the first node; and a second P-typetransistor coupled between a second power supply rail and the fourthnode, the second P-type transistor biased by the first internal biasprovided by the second circuit portion, wherein the fourth node suppliesthe output signal.
 3. The high voltage level shifter of claim 2, whereinthe first clamp circuit comprises a first diode and second diode coupledin series between the first node and fourth node;
 4. The high voltagelevel shifter of claim 1, wherein the second circuit portion comprises:a first N-type transistor coupled between a second node and a firstpower supply rail, the first N-type transistor biased by the inputsignal; a first P-type transistor coupled between the second node and afourth node, the first P-type transistor biased by the second clampcircuit at the first node; and a second P-type transistor coupledbetween a second power supply rail and the fourth node, the secondP-type transistor biased by the second internal bias provided by thefirst circuit portion.
 5. The high voltage level shifter of claim 4,wherein the second clamp circuit comprises a first diode and seconddiode coupled in series between the first node and fourth node;
 6. Thehigh voltage level shifter of claim 2, wherein the first N-typetransistor includes a backgate node coupled to the first power supplyrail.
 7. The high voltage level shifter of claim 4, wherein the firstN-type transistor includes a backgate node coupled to the first powersupply rail.
 8. The high voltage level shifter of claim 2, wherein thefirst P-type transistor includes a backgate node coupled to the fourthnode.
 9. The high voltage level shifter of claim 4, wherein the firstP-type transistor includes a backgate node coupled to the fourth node.10. The high voltage level shifter of claim 2, wherein the second P-typetransistor includes a backgate node coupled to the second power supplyrail.
 11. The high voltage level shifter of claim 4, Wherein the secondP-type transistor includes a backgate node coupled to the second powersupply rail.
 12. The high voltage level-shifter of claim 3, wherein thefirst diode and second diode are Zener diodes.
 13. The high voltagelevel-shifter of claim 5, wherein the first diode and second diode areZener diodes.
 14. The high voltage level shifter of claim 2, wherein thefirst N-type transistor, the first P-type transistor, the second P-typetransistor are metal oxide semiconductor field-effect transistors. 15.The high voltage level shifter of claim 4, wherein the first N-typetransistor, the first P-type transistor, the second P-type transistorare metal oxide semiconductor field-effect transistors.
 16. A highvoltage level shifter, the high voltage level shifter couples to receivean input signal to generate an output signal, comprising: a resistorcoupled between a first node and a first power supply rail; an invertercoupled to receive the input signal to provide an inverted input signal;a first N-type transistor coupled between a second node and a firstpower supply rail, the first N-type transistor biased by the invertedinput signal; a second N-type transistor coupled between a third nodeand a first power supply rail, the first N-type transistor biased by theinput signal; a first P-type transistor coupled between a fourth nodeand the second node, the first P-type transistor biased by the firstnode; a second P-type transistor coupled between a fifth node and thethird node, the second P-type transistor biased by the first node; afirst and second diode coupled in series between the first node andfourth node; a third and fourth diode coupled in series between thefirst node and fifth node; a third P-type transistor coupled between asecond power supply rail and the fourth node, the first P-typetransistor biased by the fifth node; and a fourth P-type transistorcoupled between the second power supply rail and the fifth node, thesecond P-type transistor biased by the fourth node, wherein the fourthnode provide the output signal.
 17. The high voltage level shifter ofclaim 16, wherein the first N-type transistor includes a backgate nodecoupled to the first power supply rail.
 18. The high voltage levelshifter of claim 16, wherein the second N-type transistor includes abackgate node coupled to the first power supply rail.
 19. The highvoltage level shifter of claim 16, wherein the first P-type transistorincludes a backgate node coupled to the fourth node.
 20. The highvoltage level shifter of claim 16, wherein the second P-type transistorincludes a backgate node coupled to the fourth node.
 21. The controllerarea driver of claim 16, wherein the first and second diodes are Zenerdiodes.
 22. The controller area driver of claim 16, wherein the thirdand fourth diodes are Zener diodes.
 23. The high voltage level shifterof claim 16, wherein the third P-type transistor includes a backgatenode coupled to the second power supply rail.
 24. The high voltage levelshifter of claim 16, wherein the fourth P-type transistor includes abackgate node coupled to the second power supply rail.
 25. The highvoltage level shifter of claim 16, wherein the first N-type transistor,the second N-type transistor, the first P-type transistor, the secondP-type transistor, the third P-type transistor and the fourth P-typetransistor are metal oxide semiconductor field-effect transistors.